Digitally Tunable CMOS Mixer Design for Adaptive RF Front-Ends

Reconfigurability and self-optimization have become essential during radio frequency integrated circuit (RFIC) design to support the growing number of devices and fast changes in the surrounding wireless spectrum. This has created the need to develop new design approaches for RFICs based on end-to-end wireless system-level performance metrics during operation in dynamically changing communication environments. This paper introduces a CMOS mixer with a wide range of digitally tunable bias current for machine learning (ML) based adaptation. The mixer is designed to become part of a self-adaptive receiver (RX) architecture that is capable of optimizing its performance in accordance to wireless channel conditions by evaluating systemlevel parameters. The proposed mixer topology has digitally tunable bias current and a programmable helper current (PHC) circuit to maintain the voltage headroom during operation with a wide tuning range. It is capable of dynamically minimizing power consumption based on performance and wireless network requirements. Post-layout simulation results show that the power consumption can be reduced up to 8x depending on momentary performance needs, while maintaining an IIP3 greater than -2.4 dBm for the entire range of operation.