Design of Delta Sigma Modulator Using Approximate Adder With Near-Normal Error Distribution For Fractional-N Frequency Synthesizer

This paper presents a novel approach to the design of Delta-Sigma Modulators (DSMs) for Fractional-N Phase Locked Loop (PLL) Frequency Synthesizers by incorporating an approximate adder characterized by near-normal error distribution. Traditional Frequency Synthesizers utilize DSMs that rely on precise adders and Pseudo-Random Binary Sequence (PRBS) generators to provide modulus inputs to multi-modulus frequency dividers for achieving Fractional-N Frequency Synthesis. The inclusion of PRBS is critical in introducing randomness in the DSM’s output, thereby mitigating frequency spurs in the output of the synthesizer. In contrast, the proposed DSM design leverages an approximate adder with near-normal error distribution to introduce the required randomness, eliminating the dependency on PRBS. This innovative design leads to substantial improvements in power efficiency, area, processing speed and improves the performance of the synthesizer. The proposed design demonstrates a reduction of approximately 44.7% in power consumption and 39.73% in area compared to conventional DSMs combined with PRBS generators when implemented in 65nm TSMC technology. The proposed design achieves comparable accuracy in output frequency, maintains similar Signal-to-Noise Ratio (SNR) and Effective Number of Bits (ENOB), and shows improvement in Spurious-Free Dynamic Range (SFDR).