Learning More Comprehensive Representations of ICs for Enhanced Routing Congestion Prediction

As Integrated Circuits (ICs) increase in complexity, there is a growing need for more comprehensive representations within deep learning approaches to support Electronic Design Automation (EDA) tasks in the backend stage, such as routing congestion prediction. However, current methods in congestion prediction often fail to fully combine both topological and geometrical information, limiting their ability to effectively represent and optimize circuits. Here we propose a novel architecture named TGFN that effectively merges topological information from the entire circuit and diverse geometrical information from layouts to enhance prediction accuracy. This model is specially designed to accommodate various data structures, integrating them into a cohesive latent representation that comprehensively models the circuit. Experimental results demonstrate that our method not only leverages both types of information effectively but also outperforms alternative baseline approaches. Notably, it achieves up to 6.87%, 11.24% and 15.96% improvements in Pear-son, Spearman and Kendall correlation coefficients respectively.