Improving Scalability of NoC-Based Neuromorphic Hardware with Compressed AER (C-AER) Protocol

Digital neuromorphic architectures use the address event representation protocol (AER), which encodes a spike into the address of it’s originating neuron. We show that, this baseline AER protocol is inefficient in network-on-chip (NoC)-based many-core designs, increasing the congestion, delay and energy consumption on the NoC. We introduce CAERPRO, a novel spike encoding protocol for many-core neuromorphic hardware. The key idea of CAERPRO is to organize the output spikes of a core (in space and time) as a single binary spike string and compress it into fewer bits using a static compression technique. We implement CAERPRO for a state-of-the-art NoC-based neuromorphic hardware and synthesize it using Synopsys Design compiler in 32nm technology. Our results using 4 workloads show that, compared to baseline AER protocol, CAERPRO reduces energy consumption on the NoC by an average 14.8× and latency of spike events by an average 9.6×. Furthermore, we show that CAERPRO compression and decompression hardware consume only 2.97% of the total power of a neuromorphic core at 1Mhz clock frequency and introduce a marginal area overhead of 0.26%.