An EF-CIFF Noise-Shaping SAR ADC with A Joint Dynamic Amplifier, Comparator and Lossless Passive Summer Structure

This paper presents a power-efficient error-feedback and cascaded-integrator-feedforward (EF-CIFF) hybrid noise-shaping (NS) successive approximation register analog-to-digital converter (SAR ADC). A joint dynamic amplifier, comparator and lossless passive summer structure is proposed in the NS SAR ADC, where a pair of capacitors is reused among the above three sub circuits. The capacitors are first employed as the load of the dynamic amplifier, then used to store the residual signal in the summer, and finally used to compose a dynamic-biased comparator. The joint structure and the fully dynamic operations make the NS SAR ADC power-efficient. The ADC is designed in a 40nm CMOS. With a sampling rate of 50MHz, the ADC achieves 81.8dB SNDR over a 3.125MHz BW in simulation. The power consumption is 190.3μW, resulting in a Schreier FoM of 184.0dB.