A PVT-Insensitive 7-Bit Coarse-Fine Ratio-Metric Digital-to-Time Converter for Fractional-N Phase-Locked Loops in 65-nm CMOS

This paper introduces a coarse-fine ratio-metric digital-to-time converter (DTC) for fractional-N phase-locked loops (PLLs). The proposed DTC exploits the period of a well-defined clock from the PLL as the time-domain reference, thereby achieving PVT-insensitive resolution. The programmable delay is achieved by setting the initial charge on a load capacitor in the pre-discharging phase. It is followed by constant-slope discharging to trigger a comparator and generate the delayed clock edge. The 4-bit MSBs of the DTC is realized by programming the discharging pulse width of the MSB of an IDAC, while the lower 3 bits of the DTC is implemented by controlling the discharging current from the IDAC over a fixed pulse width. Designed in 65-nm CMOS technology, the proposed 7-bit DTC achieves 4.72-ps resolution with a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 1.45 ps and 2.26 ps at 600-ps full-scale delay range in simulations. Over PVT variations, the DTC resolution changes by only ±0.85%. The proposed DTC consumes 720uW from 1V supply and occupies 0.0124-mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area.