An Asynchronous RISC-V Processor Utilizing a Chisel-Based Desynchronization Flow

Asynchronous circuits become an attractive alternative to synchronous circuits owing to their potential benefits such as low power consumption, and no clock distribution problems. However, handshake control and relative timing analysis make designing asynchronous circuits a complex and error-prone task. Moreover, traditional electronic design automation (EDA) tools are tailored specifically for synchronous circuits, resulting in significant manual effort when designing asynchronous circuits. To address these issues, this paper proposes a desynchronization method based on Chisel, which converts synchronous circuits into bundled-data asynchronous ones automatically. For demonstration, an open-source synchronous RISC-V processor is desynchronized to an asynchronous one, and both are implemented on Zynq7020 FPGA. The experimental results illustrate that the power consumption of Clicks for handshaking in the desynchronized processor is only 33.3% of that of the global clocks in the synchronous one. Besides, with Clicks the power consumption of memory access is reduced by 80%. Compared with previous synchronous and asynchronous RISC-V processors, the asynchronous RISC-V processor achieves up to 8.4x and 1.5x dynamic power reductions respectively.