An Incremental Σ∆ Current-to-Digital Converter with Dynamically Scalable Power Consumption and No Dead Time

This paper presents a Current-to-Digital Converter (CDC) designed for Computed Tomography (CT). The circuit, featuring a fully differential architecture, has been fabricated in a 0.35-µm-CMOS technology with a silicon area of 0.65 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 300 nJ per conversion from a nominal supply voltage of 3.3 V, with a conversion period of 200 µs. The average power consumption is reduced by 22% by applying a dynamic power consumption scaling technique based on operational amplifier slicing. The proposed CDC achieves a dynamic range of 89 dB (12.75 ENOB) over a 2.5 kHz bandwidth, leading to a Schreier figure-of-merit of 151.2 dB.