New self-calibration algorithm for programmable multi-core memristor-CMOS chip for neuromorphic computing

The advent of hybrid memristor-CMOS technologies opens an exciting alternative to implement compact neuromorphic hardware with dense layers of neurons interconnected via memristive synapses for low-power energy-efficient high-speed inference applications and online learning. However, before implementing large multi-layer networks with higher number of neurons, many practical issues should be overcome, both associated to the memristive devices and the CMOS architecture. For that, we have designed a configurable and scalable multi-core architecture based on a computing core formed by 64 pre- and 64 post-synaptic neurons densely interconnected through 4k memristors. In this work, we present a chip including 16 cores, which allow for several different combinations with a total number of 64k memristors. A test infrastucture has been implemented to configure different architectures and run experiments from a processor. A new iterative self-calibration algorithm has been proposed to compensate for mismatch variations of the critical CMOS part, and an inference experiment with larger-resolution binary images has been demonstrated as a proof of concept.