A Compact 3-Segment 15-bit Capacitive DAC with Digital Calibration for Improved Linearity

This paper proposes a novel redundancy-based approach to drastically relax the matching requirements of CDACs and employing a cost-effective digital calibration method to improve linearity. The proposed architecture features a 3-segment CDAC with two redundant bits, which effectively reduces the overall DAC area and improves the DAC’s linearity. A 15-bit version of the DAC has been implemented in TSMC 0.18 μm technology, occupying a total area of 0.010 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The design is validated through simulations in Cadence Spectre and calibration in MATLAB, resulting in worst-case integral nonlinearity (INL) and differential nonlinearity (DNL) of less than 0.5 LSB and 1 LSB, respectively, across 200 Monte-Carlo iterations.