A 0.6V Digital-intensive Pulse Injection 32-kHz Crystal Oscillator Using Stacked Logic Gates

This paper introduces an ultra-low-power 32kHz pulse injection crystal oscillator (PIXO) using a reference-free stacked inverter chain to generate the delay signal for energy injection. If the power consumption of both the pulse driver and the inverter-based delay generation circuits is considered, analysis reveals that the closer the injection happens at the peak and valley of the output waveform, the lower the system power efficiency. The proposed stacked logic gates can generate an injection pulse that is 48° away from the zero-crossing point of the output waveform without resorting to the process- and temperature-sensitive pico-ampere-level current reference and duty-cycle-correction loop for injection timing control. The proposed PIXO can properly operate across −40°C to 120°C at five process corners (TT/SS/SF/FS/FF). Implemented in a 65nm CMOS technology, at a 0.6V voltage supply, post-layout simulations verify that the PIXO achieves 1.2nW power consumption at a 32kHz injection rate at 25°C. Thanks to its digital-intensive architecture, the PIXO occupies only 0.0069mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area.

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Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11044069
Primary Topic
Acoustic Wave Resonator Technologies
Type
article
Field-Weighted Citation Impact
0.00

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article

A 0.6V Digital-intensive Pulse Injection 32-kHz Crystal Oscillator Using Stacked Logic Gates

Jun Yin, Zhizhan Yang, Pui‐In Mak, Rui P. Martins
Acoustic Wave Resonator Technologies
article

A 0.6V Digital-intensive Pulse Injection 32-kHz Crystal Oscillator Using Stacked Logic Gates

Jun Yin, Zhizhan Yang, Pui‐In Mak, Rui P. Martins
article en

Abstract

This paper introduces an ultra-low-power 32kHz pulse injection crystal oscillator (PIXO) using a reference-free stacked inverter chain to generate the delay signal for energy injection. If the power consumption of both the pulse driver and the inverter-based delay generation circuits is considered, analysis reveals that the closer the injection happens at the peak and valley of the output waveform, the lower the system power efficiency. The proposed stacked logic gates can generate an injection pulse that is 48° away from the zero-crossing point of the output waveform without resorting to the process- and temperature-sensitive pico-ampere-level current reference and duty-cycle-correction loop for injection timing control. The proposed PIXO can properly operate across −40°C to 120°C at five process corners (TT/SS/SF/FS/FF). Implemented in a 65nm CMOS technology, at a 0.6V voltage supply, post-layout simulations verify that the PIXO achieves 1.2nW power consumption at a 32kHz injection rate at 25°C. Thanks to its digital-intensive architecture, the PIXO occupies only 0.0069mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area.

University of Macau (MO)
Science and Technology Development Fund
Affordable and clean energy
Openalex Percentile: Top 86%
Acoustic Wave Resonator Technologies
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