A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees

This paper presents a 56-Gb/s 3-tap feed-forward equalizer (FFE) four-level pulse-amplitude modulation (PAM-4) transmitter (TX) frontend for wireline applications. The proposed transmitter frontend operates at a 0.85-V termination voltage utilizing external surface-mounted (SMT) bias-tees. Unlike conventional tail-less current-mode logic (CML) drivers with variable gate biases, the transmitter frontend employs shunt-FFE for fewer variations in output common-mode levels. The design is fabricated in 40-nm CMOS technology and occupies 0.021 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The proposed PAM-4 transmitter design operating at 56 Gb/s consumes 22.0 mW from 0.85-V supply voltage, achieving 0.39-pJ/bit energy efficiency.