NAME: NoC-based Accelerators Mapping Exploration for High Performance DNN Inference

The rapid advancement of deep learning, with increasingly large deep neural networks (DNNs), has led to the use of multi-core parallel processing in accelerators, utilizing Network-on-Chip (NoC) for interconnection. However, while multi-core architectures improve computational performance, they also increase data movement overhead. This paper analyzes NoC traffic patterns during DNN processing and explores mapping optimization to reduce computational and communicational overheads. We propose NoC-based Accelerators Mapping Exploration (NAME), an automated mapper for generating high-performance task mappings for NoC-based accelerators. NAME balances computational and communication overheads by dividing DNNs into scalable groups and interleaving NoC link usage, reducing traffic bottlenecks. Experiments show that NAME reduces execution time by up to 82% and 52%, respectively, compared to fixed mapping and the state-of-the-art framework AOME (Autonomous Optimal Mapping Exploration).