A Fast Transient FVF LDO With Improved Gate Buffer and Level Triggered Transient Enhancement Circuit in 22 nm process

This paper presents a fast transient flipped-voltage-follower-based low-dropout regulator (FVF LDO) with improved gate buffer and level-triggered transient enhancement circuit (LTTEC) in a 22 nm process. The fast loop composed of an FVF and the improved gate buffer exhibits ultra-high bandwidth and high slew rate. The proposed LTTEC can supply additional sourcing or sinking current to reduce the undershoot or overshoot during load transitions. The introduced bulk driven technique can effectively improve the power supply rejection (PSR) performance. The proposed LDO achieves 0.25ns response time with simulated 40.0 mV undershoot voltage and 36.7 mV overshoot voltage for the load current transition between 100 µA and 20 mA within 0.1 ns.