Low Power Crypto-chip Design for IoT Applications Based on Systolic AES Algorithm

The need for safe, energy-efficient encryption techniques is essential in the rapidly growing Internet of Things (IoT) space in order to safeguard data on devices with limited resources. In this paper, a low-power cryptography circuit for Internet of Things applications is designed and implemented utilizing the Systolic AES algorithm on the PYNQ Z2 FPGA platform in Verilog using the AMD Vivado IDE. The approach addresses the increasing demand for energy efficient cryptographic systems in every industry and day to day life that can ensure data security in resource constrained IoT devices. The Systolic AES algorithm known for its parallel processing efficiency as its implemented to optimize encryption performance at the same timing minimizing power consumption. The design flow includes algorithm synthesis, FPGA implementation and a comprehensive analysis of critical metric including timing, resource utilization and power consumption. Hardware integration is achieved using a CP2102 UART module for real-time data transfer and validation. The experimental results demonstrate the system’s capability to significantly reduce power consumption, achieving a total on-chip power of 0.256 W while maintaining robust encryption throughput. The key FPGA resource utilization such as slice LUTs and registers is optimized for scalability and efficiency. The work highlight’s the effectiveness of systolic architecture in low-power cryptographic designs making it a very promising solution for securing IoT applications.