Performance and Parameter Optimization of GaN/InN/GaN TFET for Low-Power Applications in Sub-10nm Technology nodes

As the scaling of traditional MOSFETs approaches fundamental limits, Tunnel Field-Effect Transistors (TFETs) have gained attention due to their potential for ultra-low-power applications. Unlike MOSFETs, TFETs leverage band-to-band tunnelling (BTBT) to achieve sub-threshold slopes (SS) below 60 mV/decade, enabling significant reductions in power consumption. In this work, a TFET design using a heterostructure of GaN/InN/GaN has been proposed to overcome the limitations of conventional silicon-based and wide-bandgap material-based TFETs. The narrow bandgap of InN (0.7 eV) facilitates efficient tunnelling, while GaN’s wide bandgap (3.4 eV) provides superior electrostatic control and reduces off-state leakage.Key performance metrics have been calculated through detailed simulations such as the sub-threshold slope, on/off current ratio, and threshold voltage. The proposed GaN/InN/GaN het-erostructure TFET demonstrates enhanced tunnelling efficiency, a steep SS (potentially below 40 mV/dec), and a high on/off ratio exceeding 108 . These advantages make it highly suitable for low-power and high-performance applications, particularly in sub-10 nm technology nodes. This study underscores the viability of GaN/InN/GaN TFETs for next-generation semiconductor devices, with applications in ultra-low-power logic, high-frequency analog circuits, and wearable electronics.