An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces
This paper presents a duobinary transceiver designed for low-power and high-speed serial interfaces. The proposed circuit can simply implement by using novel architecture of duobinary precoder and decoder. The transceiver was designed in 28nm CMOS technology and verified through the post-layout simulation. And the measured energy efficiency is 1.12pJ/bit at 21Gb/s.
Authors
- Won‐Young Lee
- Seul-Ki Han
Institutions
- Seoul National University of Science and Technology (KR)
Publication Details
- Published
- 2025-05-25
- DOI
- https://doi.org/10.1109/iscas56072.2025.11044001
- Primary Topic
- Semiconductor Lasers and Optical Devices
- Type
- article
- Field-Weighted Citation Impact
- 0.00