Pioneering 8-bit Comparator Architecture with Independent (INDEP) Gate Control

This paper presents a novel 8-bit comparator architecture designed using the Independent Gate Control (INDEP) technique to enhance speed and energy efficiency. The proposed design integrates INDEP with CMOS logic gates, effectively minimizing propagation delay and reducing power consumption by 40.93% compared to conventional comparators. By optimizing conduction paths and controlling transistor switching, the design achieves faster data comparison while maintaining low power dissipation. Simulations conducted in Cadence Virtuoso validate the improved performance, demonstrating the comparator’s suitability for energy-efficient and high-speed applications such as embedded systems and digital processors.