A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration

Memory-augmented neural network (MANN) has gained attention as a pivotal solution for few-shot learning (FSL). Among the candidates for associative memory in MANN accelerators, spin-transfer torque magnetic random-access memory (STT-MRAM) stands out for its compact cell area, long data retention time, and excellent scalability. In this paper, we propose an STT-MRAM near-memory computing (NMC) macro for MANN acceleration. The macro contains following innovations: 1) An array-level parallel computing architecture for L1 distance calculation. 2) A low-area-overhead memory-invert coding technique to reduce write energy consumption. 3) A configurable dynamic offset-compensation sense amplifier (CDOC-SA) to improve classification accuracy. Fabricated in 40nm CMOS process, our macro demonstrates an energy efficiency of 6.47 TOPS/W, achieving the classification accuracy of 98.3% and 93% for 8-way-5-shot tasks and 16-way-5-shot tasks on the Omniglot dataset.

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Published
2025-05-25
DOI
https://doi.org/10.1109/iscas56072.2025.11043262
Citations
1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.73
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A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration

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Advanced Memory and Neural Computing
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article

A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration

Zizhao Ma, Shao Hao Wang, Shengchao Zhou, Tai Min, Yufeng Xie, Hongrui Meng, Yajun Wu
article en
1 citations

Abstract

Memory-augmented neural network (MANN) has gained attention as a pivotal solution for few-shot learning (FSL). Among the candidates for associative memory in MANN accelerators, spin-transfer torque magnetic random-access memory (STT-MRAM) stands out for its compact cell area, long data retention time, and excellent scalability. In this paper, we propose an STT-MRAM near-memory computing (NMC) macro for MANN acceleration. The macro contains following innovations: 1) An array-level parallel computing architecture for L1 distance calculation. 2) A low-area-overhead memory-invert coding technique to reduce write energy consumption. 3) A configurable dynamic offset-compensation sense amplifier (CDOC-SA) to improve classification accuracy. Fabricated in 40nm CMOS process, our macro demonstrates an energy efficiency of 6.47 TOPS/W, achieving the classification accuracy of 98.3% and 93% for 8-way-5-shot tasks and 16-way-5-shot tasks on the Omniglot dataset.

Fudan University (CN), Shanghai Fudan Microelectronics (China) (CN), State Key Laboratory of ASIC and System, Fuzhou University (CN), Xi'an Jiaotong University (CN)
Affordable and clean energy
Openalex Percentile: Top 27%
Advanced Memory and Neural Computing
0.73
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