Design Considerations for a Closed-loop Digital Class-D Audio Amplifier

Class-D audio amplifiers with a digital feedback path are advantageous when from a digital audio input. The input DAC, which needs to support the full audio resolution, is avoided. A digital loop filter’s transfer function can be realized accurately. Therefore stability can be maintained while maximizing the loop gain within the signal band. On the other hand, a high-resolution ADC is required in the feedback path. The constraints and requirements on the digital loop filter and the ADC are presented. The resulting digital filter can be accommodated within a 100 MIPS digital signal processor. The amplifier is designed to deliver an output power of 4 W to an 8 Ω speaker load. The switching frequency of the power stage is 384 kHz. The digital pulse width modulator operates with a clock frequency of 24.576 MHz. The feedback path uses a continuous time delta-sigma analog-to-digital converter with a sampling frequency of 6.144 MHz and an oversampling ratio of 128. The simulated peak SNDR is 93 dB in a 20 kHz bandwidth. Measurement results are presented from a hybrid prototype with an FPGA-based digital loop filter, discrete-component H-bridge driver and antialias filter, and a continuous-time delta-sigma ADC IC.