Memristor-Assisted CDAC Background Calibration Scheme for SAR ADCs

This paper proposes a V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf>-compensated memristor-assisted CDAC background calibration scheme for Nyquist SAR ADCs. The proposed CDAC is implemented in a 12-bit 5 MS/s asynchronous SAR ADC featuring a V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cm</inf>-based switching scheme and designed using a standard 65 nm CMOS process. Capacitor mismatches are detected by introducing a redundant bit, which evaluates the sign of the mismatch error. This error is then calibrated through a feedback loop using voltage dividers with four integrated memristors. These programmable voltage dividers generate a compensating voltage that is added to or subtracted from the ADC reference voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf>) based on the sign of the mismatch error. Consequently, the adjusted V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ref</inf> compensates the CDAC output level to reduce non-linearity induced by capacitor mismatches. Simulation results validate the feasibility of optimizing non-linearity in moderate/high-resolution SAR ADCs (12-bit in this study) caused by capacitor mismatches, improving the signal-to-noise-and-distortion ratio (SNDR) from 41.85 dB to 65.98 dB with memristor-assisted analog circuits. The proposed SAR ADC occupies 0.0153 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area according to the layout floorplan, making it a promising candidate for miniature/large-scale sensor interface application.