Analysis and Comparison of various Leakage power control techniques for 6T SRAM using 18 nm FinFET Technology

The dissipation of leakage power increases sharply with the continuous growth of metal oxide semiconductor (MOS) devices, hence increasing the overall dissipation of power. This is due to a rise in short-channel effects. A FinFET device can decrease short-channel effects, which also lowers power dissipation. This work proposes a 6T SRAM mechanism based on short-gate FinFET (Fin type field effect transistor) at an 18nm technology node using LCNT (Leakage Control NMOS transistor) LCPT (Leakage Control PMOS transistor) and LECTOR (Leakage Control TransistOR) using cdsffmpt (An 18nm FinFET Predictive process design kit in Cadence virtuoso). A comparison analysis using one without the Leakage control technique is given. The simulated results show that an SRAM based on LCNT technology reduces the average power dissipation and the power delay product (PDP) very significantly, compared to other leakage control approaches.