Design and Simulation of Discrete Cosine Transform Using 10T Transistors Adders

The Discrete Cosine Transform (DCT) is a fundamental tool in image compression, widely used in standards like JPEG, because it helps to concentrate most of the image’s energy into fewer co-efficients. However, the conventional DCT relies on the Multipliers, which increases power consumption, area and delay. This paper proposes a hybrid full adder design, created by analyzing and combining various CMOS adder styles. Among these styles, the Proposed GDI XOR – based full adder is used for its efficiency and low power usage. The proposed full adder has its area reduced by 16.6% which is compared with an existing DCT implementation to evaluate improvements in power consumption, delay, and image quality (PSNR).