A Linear-Regression-Assisted Trimming Scheme for CMOS Voltage Reference

This work proposes a single-point linear-regression-assisted trimming method for a MOSFET-based voltage reference to reduce operation verification complexity. By obtaining the correlation between the input features at a unique temperature and the output voltages across the operating temperature range from layout-aware Monte-Carlo simulations, we can build the linear regression model to predict the profile of the voltages across the temperature range based on eight input features. Hence, we can apply the appropriate trimming code on the circuits, avoiding time-consuming temperature characterization. We design the voltage reference in 65nm CMOS and obtained 8,000 sets of simulation data to train the regression model. Validated through simulation, we reduce the temperature coefficient of the voltage reference to 64.7ppm/°C using the proposed scheme, 26% lower than that of the conventional 2-point trimming, evincing the efficiency and accuracy of the linear-regression-assisted trimming.