Design and Performance Analysis of 14T Low Power and Less Area 1-bit Hybrid Full Adder

Adders play an important role in performing arithmetic operations. In traditional CMOS techniques the transistor count is higher than in logics such as pass transistor logic but the output power is much more efficient than those logics. Hence, we adopt methods like, Complementary Pass Transistor Logic, Hybrid logic, etc. The proposed architecture primarily focuses on reducing area with minimal deviations while enhancing power and delay values. The proposed architecture utilizes 1-bit hybrid logic consisting of 14 transistors examined by evaluating 90-nm CMOS technology and stimulated in Ltspice. The analysis was conducted with a supply voltage of 0.8V consuming average power of 0.381 microWatt.