Mathematical Modeling of Contention and Power Efficiency in Wormhole Routers for Scalable NOC Systems

This study focuses on the design and analysis of a wormhole router within a 4 × 4 network-on-chip (NoC) mesh topology, highlighting its role in efficient on-chip communication. The router's performance is evaluated using metrics such as latency, throughput, contention probability, buffer utilization, and power consumption. Results show that total latency, driven by routing, switching, and blocking delays, reached 28.8 cycles for 4 hops at 60% traffic intensity. Throughput peaked at 1.28 Gbps per virtual channel at moderate traffic loads, but declined sharply under high contention. The buffer utilization was 37.5% for a buffer depth of eight flits, and the total power consumption was 9.84 μW, dominated by buffer operations. These findings emphasize the need to optimize buffer usage, congestion management, and energy efficiency, making the wormhole router a scalable and effective solution for NoC architectures.