Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement with Minimal Data Input

We present an ML-driven framework for predicting circuit performance metrics, bridging the gap between schematic and layout simulations, multi-process corner analysis, and measured silicon data. We focus on 14nm and 5nm FinFET-based ring oscillators, collecting data across varying supply voltages, temperatures, and process corners. Using three baseline ML models—XGBoost, Random Forest, and a Neural Network—we simulate real-world design scenarios where parameter fine-tuning may not always be feasible. Key tasks include predicting layout performance from schematic data, performance prediction across process corners, and predicting measured chip performance via transfer learning. Our results show that these models can achieve less than 5% mean absolute percentage error (MAPE) for power and frequency prediction while reducing required simulations by more than 2×. In migrating from 14nm to 5nm, XGBoost and Neural Network achieve high accuracy (>0.99 R<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) using just 10% of 5nm simulations. This framework offers a promising approach to accelerating circuit design across technology nodes, reducing simulation costs while maintaining accuracy in predicting performance.