A 0.4V Relaxation Oscillator featuring Double Capacitor-Charging Headroom in CMOS 65nm

Low-Power fully-integrated oscillators are the cornerstone of Internet-Of-Things devices due to their compactness, high energy-efficiency, and scalability. This paper presents a relaxation oscillator featuring double capacitor-charging headroom by applying chopping on the capacitor. Such an increase in the charging headroom soothes the frequency instability attributable to the comparator and logic gate’s delay, culminating in a more stable frequency output amid voltage and temperature variations. We designed and fabricated two 0.4V relaxation oscillators (803kHz and 428kHz) in the TSMC 65nm process. The measured temperature coefficients are 164 and 106 ppm/°C (averaged from 10 samples) across −20 to 120°C for the 803kHz and 428kHz relaxation oscillators, and the line sensitivities are 15.8%/V and 14.4%/V across 0.35 to 0.5V. Such results are improved by >1.8× and >11× compared with the reference oscillator with regular charging headroom. The oscillators’ long-term stabilities are 150 and 110 ppm with a 0.1s gating interval.