Parametric Variation Analysis of FD-SOI MOSFET for High-Speed IC Design Applications

Traditional bulk MOSFETs experience several short channel phenomena in the nanoscale domain. An SOI (Silicon-on-Insulator) MOSFET represents the enhanced nanoscale device versions of MOSFETs that have appeared in recent years owing to its inherent benefits of extremely low junction capacitance, significantly reduced leakage currents, increased drain currents and so on. The present work centers on conducting a comprehensive study on FD (Fully Depleted)- SOI MOSFET in order to explore its performance in terms of variations in metal work function, source doping, top semiconductor layer and gate oxide thickness using SILVACO ATLAS TCAD. Present analysis focuses on simulated results related to several key electrical characteristics, including energy band diagrams, gate and drain capacitance, I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>, variations in threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf>), sub-threshold swing (SS). Present study exhibits that the threshold voltage decreases with a rise in source doping concentration, and it rises with an increase in top semiconductor layer thickness, metal work function and gate oxide thickness, measuring a threshold voltage of 0.37V for a 5 nm top semiconductor layer. It also reports a subthreshold swing (SS) of 42.3 (mV/dec) for 2 nm gate oxide thickness.