IP core generation and ASIC chip implementation of Discrete Wavelet Transform for Medical Images: A Comparative Analysis

This paper presents the implementation and evaluation of the Discrete Wavelet Transform (DWT) for medical image fusion, utilizing Verilog in Vivado and Cadence Innovus tools. The design was synthesized and implemented on the Pynq Z2 FPGA platform and optimized for 90 nm technology. Power consumption, resource utilization, and timing characteristics were thoroughly analyzed to ensure efficient hardware realization. The Vivado analysis revealed a total on-chip power consumption of 0. 352W, with significant contributions from I/O and dynamic power components. The Cadence Innovus results highlighted the efficient use of 2441 standard cells, achieving optimal area utilization with a total cell area of 16,517 µm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Despite a setup timing violation of -1716 ps, the design demonstrates feasibility for high-performance medical image fusion applications. The proposed implementation achieves an efficient balance between computational accuracy, resource usage, and hardware efficiency, offering a practical solution for real-time medical diagnostics or applications in image compression, feature extraction, and biomedical imaging.