High Performance Reverse Converter Design Using Modified Brent-Kung EAC Adder

In this paper, a high performance reverse converter is designed using modified Brent-Kung EAC (End Around Carry) adder for Residue Number System (RNS) applications. Modulo adder is the basic component employed in reverse converter design. The Hybrid Modular Parallel Prefix Excess-One (HMPE) structure has modified excess-one unit and a multiplexer. The proposed adder, does not requires modified excess-one unit and multiplexer. Due to this modification, It achieves high speed, less area and low power when compared to the existing design. The superiority of this proposed adder based reverse converter for moduli sets were validated using Altera Quartus II tool. The reverse converter based on developed adder has 31.96% reduction in PDP and 8.57% reduction in area when compared to the HMPE & HRPX-BK structure based reverse converter.

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Publication Details

Published
2025-04-23
DOI
https://doi.org/10.1109/raeeucci63961.2025.11048213
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

High Performance Reverse Converter Design Using Modified Brent-Kung EAC Adder

A Vidya, Thiruvenkadam Krishnan, P. Mani, Parthibaraj Anguraj et al.
Low-power high-performance VLSI design
article

High Performance Reverse Converter Design Using Modified Brent-Kung EAC Adder

A Vidya, Thiruvenkadam Krishnan, P. Mani, Parthibaraj Anguraj, S. Saravanan
article en

Abstract

In this paper, a high performance reverse converter is designed using modified Brent-Kung EAC (End Around Carry) adder for Residue Number System (RNS) applications. Modulo adder is the basic component employed in reverse converter design. The Hybrid Modular Parallel Prefix Excess-One (HMPE) structure has modified excess-one unit and a multiplexer. The proposed adder, does not requires modified excess-one unit and multiplexer. Due to this modification, It achieves high speed, less area and low power when compared to the existing design. The superiority of this proposed adder based reverse converter for moduli sets were validated using Altera Quartus II tool. The reverse converter based on developed adder has 31.96% reduction in PDP and 8.57% reduction in area when compared to the HMPE & HRPX-BK structure based reverse converter.

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Low-power high-performance VLSI design
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