Artificial Intelligence based Test Vector Reordering for Optimal Test Power Reduction

Analysis of Systems-on-Chip (SoC) built around cores with IP faces significant challenges in minimizing test power, especially during external testing. Techniques such as "don’t care bit filling" and "test vector reordering" have proven effective for reducing switching activity without requiring modifications to the internal structure or employing specialist tools for testing, making them suitable for IP cores with hidden structures. This paper proposes a Low Power Artificial Intelligence-Based Vector Reordering (LPAVR) method which combines the A* algorithm for Path Finding and Minimum Hamming Distance together to optimize test vector sequences and minimize capture power at the input side. The proposed AVR method fills don’t care bits in the test vectors strategically and reorders them that is fed into the design under testing. A series of X bits is replaced based on adjacent non-X entries to ensure uniformity and minimize transitions. Empirical results demonstrate an average switching activity reduction of 34% for combinational circuit and 18% for sequential circuits. By optimizing the order of test vectors and strategically filling X bits, AVR enhances the low-power testing process for combinational circuits. This approach effectively addresses the increasing power minimization challenges posed by process technology scaling, providing a practical solution for test engineers and SoC designers.