A Dynamic Biasing Circuit for Low-Power Push-Pull Input Buffer

This paper presents a fast dynamic biasing technique for push-pull input buffers in high-speed ADCs. It introduces a coupling capacitor to the gate of the buffer to pull down its overdrive voltage after sampling, thus turning it off in idle time. Due to the complementary structure, the kickback to the input from the gate of PMOS and NMOS can be canceled out, introducing no perturbation. The proposed technique is implemented and validated in a 28nm CMOS process with a push-pull source follower input buffer which works under a 1.2 V power supply with a bias current of 7.5mA on one side. The dynamic biasing circuit shuts down the single-ended current to 2mA after sampling, reducing the average current by 40% with 50% duty cycle.