Low-Clock Latency SDRR-Based AES

Recent hardware designs of the Advanced encryption standard (AES) employ randomized Double Rate Registers (DRRs) to counter Power Analysis Attacks (PAAs). This paper introduces a low output latency hardware architecture of AES based on DRRs. The proposed design does not duplicate the data-path and reduces the clock latency by utilizing the rising and falling edges of the clock. The proposed architecture reduces encryption clock latency by 25% and achieves the best hardware efficiency of 0.87 Mbit/s × LUT compared to the existing DRR based AES counterparts when realized on Xilinx xc7a100tftg256-2 FPGA device. In addition to its superior hardware and time complexities, the proposed AES hardware architecture demonstrates similar protection to the existing DRR based AES designs when tested against Correlation power analysis attacks (CPAs) using ChipWhisperer.