A 1/10 DTC Range Reduction Technique in a Fractional-N MDLL Using a Reference Triggered Ring Oscillator

In this brief, we present a fractional-N multiplying delay locked loop (MDLL) which uses a reference triggered ring oscillator (RTRO) as a coarse digital-to-time converter (DTC) to reduce a required fine DTC range by 1/10, improving its linearity. The RTRO’s period is a programmed offset from the MDLL period so that each RTRO cycle effectively adds a delay to the reference clock. As a result, the fine DTC range only needs to cover the programmable coarse step, allowing > 9x range reduction, relaxing the design requirements of the DTC. The RTRO and MDLL periods are regulated by frequency locked loops (FLLs) that use a bang-bang phase detector (BBPD) to detect errors. Delay Locked Loops (DLLs) are used to regulate the DTC delays and absorb the offsets introduced by each BBPD. An LMS algorithm-based background calibration is used for correcting the fine DTC gain. To prove the concept, we designed the MDLL in a 65nm CMOS process. Verilog simulation with block-level models based on parasitic-layout transistor-level simulation results are used to evaluate the performance. A RMS jitter of 141.3fs was achieved at 3.00005GHz with a 50MHz reference clock, achieving a -246.7 dB FoM. The worst case fractional spur and reference spur are -69.2 dBc and -55.5 dBc, respectively.