All-Digital Open-Loop 2^nd-order Pulse Shaping Filter VCO-based ADC

The focus of this paper is to demonstrate first that high order noise shaped data converters can be digitally generated in open loop architectures, avoiding both stability problems and complex analog loops, and second that a low power PLL design can be used as the clock generator for such VCO-based ADCs. An open-loop 2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup>-order VCO-based ADC is proposed by means of a digital approximation of the pulse shaping filter to a second-order sinc function. The pulse shaping filter is digitized with a time reference signal used to quantize time differences and taken from a low power PLL implemented on silicon using a 65nm CMOS design node. The proposed architecture is firstly described theoretically and afterwards is experimentally tested for an audio bandwidth application. A model of the PLL output phase noise is measured in the test chip and is used in a simulation platform to check the real performance that could be experimentally achieved. The results prove that the time reference requirements can be met with low power architectures, achieving negligible SNR degradation and opening up the possibility of implementing scalable, low power and small area all-digital N<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup>-order VCO-based ADCs.