A Reference-less All-digital BPSK-based Clock and Data Recovery Circuitry for Die-to-Die Interfaces

In theory, the binary phase shift keying (BPSK) modulation requires the least SNR to achieve a given bit error rate. Hence, it is an appealing alternative to implement the SerDes transceivers for die-to-die connections. This paper proposes an all-digital BPSK clock and data recovery (CDR) circuit design that requires neither a PLL nor a reference clock. The proposed CDR consists of a digitally controlled delay lock loop (DCDLL) that delays the BPSK input by T/4, T/2, and T, where T is the symbol period. The CDR manipulates these delayed BPSK signals with digital gates to recover the data first. Then, the recovered data are used to recover the clock. Consequently, the recovered clock always traces the recovered data, allowing the CDR to tolerate considerable input jitters. The all-digital and PLL-free implementation results in a compact and low-power CDR. The experimental results of a test chip fabricated in 90nm CMOS show the BPSK CDR is as tiny as 0.00111mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. At an effective data rate of 3Gb/s, the BPSK CDR consumes 1.75mW, corresponding to an FoM of 0.58pJ/bit.