A Resource-efficient Dually-addressable Memory Architecture on FPGA

To address memory throughput challenges in contemporary computing systems, content-addressable memories (CAMs) and dually-addressable memories (DAMs) are implemented to enable fast search operations. However, current FPGA implementations severely lack dual addressability with high resource costs. In this paper, we present a resource-efficient Block RAM (BRAM)-based DAM architecture on FPGA to enable effective database manipulations without data duplication. An example design of size 8×512×36 bits is implemented on Xilinx Virtex-7 FPGA with 4 BRAM36, 683 LUTs, and 248 FFs, reaching a 100% BRAM to DAM efficiency.