Modified DDCCTA based Memristor Emulator circuit for Incremental and Decremental mode

This paper introduces a novel memristor emulator (MRE) designed using a modified Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA). The proposed architecture efficiently supports floating and grounded configurations without requiring additional sub-circuit elements, enabling seamless compatibility with Complementary Metal-Oxide-Semiconductor (CMOS) technology. The MRE effectively replicates frequency-dependent pinched hysteresis loops (PHLs) at 40 MHz while exhibiting non-linear resistance characteristics, preserving the essential properties of a memristor. Furthermore, pulse-based simulations confirm its non-volatility by maintaining stable memductance values during non-pulse intervals. Implemented using the TSMC 0.18µm process parameters, the emulator demonstrates excellent power efficiency, consuming just 6.6 mW. This design offers a promising solution to challenges related to power consumption, high-frequency operation, and integration, making it highly suitable for energy-efficient signal processing and neuromorphic applications.