A 112Gb/s Analog-MUX-based PAM-4 Transmitter with Inherent 2-tap FFE in 65nm CMOS

For wireline transmitters (TX), the traditional architecture would introduce a large amount of parasitic capacitance and reduce the bandwidth of the output stage. Strict timing constraints for retiming units in FFE arrays would also limit speed and consume extra power. In this paper, we propose an analog-MUX-based architecture with a small capacitance load of output drivers and inherent FFE without strict timing constraints. Only one full-speed node makes it easy to use inductors to extend bandwidth. The expanded output bandwidth ensures the TX to reach a comparable operating speed with advanced technology even in traditional planar technologies. A CML clock path with switched inductors is proposed to cover the full frequency band. Implemented in a 65nm CMOS process, the TX with 112Gb/s PAM4 data rate and 3.14pJ/bit efficiency is achieved. The data rate can be further improved with more advanced process nodes.