A Reliability-Aware Replacement Policy for STT-MRAM Caches in Server-Class Processors

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Spin-transfer torque magnetic RAM</i> (STT-MRAM) has several advantages over conventional SRAM technology in on-chip caches, such as low leakage, soft error tolerance, and high density and scalability. These advantages make it the most promising nonvolatile memory for SRAM replacement. However, STT-MRAM cache memory faces two main reliability challenges in emerging <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nanoscale</i> technology nodes, i.e., <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">retention failure</i> and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">read disturbance</i>. Because of the lower data access rate in the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">last-level caches</i> (LLCs) compared to the higher cache levels, as well as the higher contribution of read accesses, these two reliability challenges have become severe in the LLCs of server-class processors. The existing approaches to overcome these challenges impose significant area and performance overhead or adversely affect the other failure types. In this article, we first investigate the parameters that affect the reliability of STT-MRAM-based LLCs due to the retention failure and read disturbance. Our investigation shows that 1) the duration of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dead dirty blocks</i> is the main contributor to the retention failure rate of STT-MRAM LLCs while 2) the high number of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">risky</i> reads, i.e., those that can affect the cache reliability, in the dirty blocks is the main contributor to the read disturbance. Based on these observations, we propose a simple yet effective cache replacement policy, called <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><u>Re</u>tention <u>f</u>ailur<u>e</u> and <u>re</u>ad disturba<u>nce</u> reduction</i>, to decrease the length of dirty intervals and the number of reads, which results in a significant reduction in retention failure and read disturbance rate. Our evaluations demonstrate that the proposed replacement policy cuts down the probability of retention failure and the number of risky reads per dirty block by 56% and 61%, respectively. The area overhead of this scheme is negligible (0.2%) with no adverse effect on the energy consumption.