Halfbex: A RISC-V Microarchitecture with Narrow Data Path for Improved Energy Efficiency

We propose a 32-bit RISC-V processor supporting the RV32IC instruction set. The data path width of the core has been reduced to 16 bits to save power and silicon area. By that means, instructions are forced to complete in multiple cycles. Through optimizations taking advantage of instruction information and processed data a large number of unnecessary execution cycles can be pruned. Thereby, the throughput is significantly increased. Extensive evaluation of the optimizations validate the efficiency of the proposed microarchitecture. Moreover, a post-layout simulation of the placed-and-routed design confirms the benefits of the architecture, saving between 27% and 57% of energy compared to the Ibex processor on tested benchmarks.