A Resonator-optimized 15mW 18-50GHz Quad-core-six-mode VCO with 204dBc/Hz FoM<sub>T</sub> and 0.058mm<sup>2</sup> Compact Area in 40nm CMOS
A quad-core-six-mode broadband low-phase-noise low-power-consumption VCO is proposed in this paper. The design innovates by augmenting a quad-core-quad-mode oscillator to a six-mode configuration with the proposed side mode controller (SMC) to extend the frequency tuning range (TR). The parasitic components of the resonator are also studied to optimize the total performance of the VCO. A 3-bit constant R<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sup>C switchable capacitor array (SCA) is integrated to further enhance frequency coverage. Simulated in SMIC 40nm CMOS technology, the VCO, along with the buffer, demonstrates a maximum phase noise (PN) of -97 dBc/Hz@1MHz and an optimized figure-of-merit (FoM) of 185 dBc/Hz@1MHz, alongside a maximum FoMT of 204 dBc/Hz@1MHz. This design achieves a substantial TR of 91.8%, covering 18.7 to 50.3 GHz, with a consistent output power of more than -8 dBm across the entire band.. The power consumption is maintained at an efficient 15 mW, operating from a 700 mV supply.
Authors
- Haiping He (ORCID: https://orcid.org/0000-0001-8246-0286)
- Changqi Zhou
- Hao He
- Zhijian Chen (ORCID: https://orcid.org/0000-0002-5844-0135)
- Jianbo Huang (ORCID: https://orcid.org/0000-0002-3444-369X)
- Shiguang Zhong
Institutions
- National University of Singapore (SG)
- South China University of Technology (CN)
Publication Details
- Published
- 2025-05-25
- DOI
- https://doi.org/10.1109/iscas56072.2025.11044238
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China