Live Demonstration: A Scalable CNN Accelerator SoC With a Cost-Effective Chip-to-Chip Adapter

In this demonstration, we present a system-on-chip (SoC) designed to support scalable CNN acceleration at a low cost. The SoC features a cost-effective chip-to-chip adapter that enables scalable performance improvements with minimal design costs. This adapter manages chip-to-chip synchronization and data scheduling, effectively reducing chip-to-chip latency overhead. The SoC is implemented using the Silterra 130-nm CMOS technology with a chip size of 6.3×6.3 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.