A 0.8V 8b-ENOB 80kS/s-20MS/s Passive Noise-Shaping SAR ADC For Ultra Low-Power Receivers

This paper presents a second-order passive noise-shaping SAR ADC for low-power receivers, aimed at reducing the power consumption of the anti-aliasing filter and input buffer to enhance energy efficiency. A self-synchronized asynchronous logic with system control and standby mode is proposed, allowing the ADC to maintain high energy efficiency across a wide sampling range of 80kHz to 20MHz. Additionally, a dynamic control logic for the splitting monotonic switching DAC is proposed. Fabricated using a 55nm CMOS process, the ADC occupies only 0.012mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Measurement results demonstrate that, at a supply voltage of 0.8V and an oversampling ratio (OSR) of 5, the ADC achieves an effective number of bits (ENOB) between 7.6 and 8 bits across the specified sampling rates. Power consumption scales linearly from 105nW to 18.47µW with frequency, offering an energy-efficient solution for low-power receivers.