Analysis and Design of ULV DIGOTAs in 16 nm CMOS FinFET

<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>Three Digital Operational Transconductance Amplifier (DIGOTA) topologies, i.e. the standard DIGOTA, a Schmitt-Trigger-Based DIGOTA (ST-DIGOTA) and a DIGOTA with a Floating-Inverter input stage (FI-DIGOTA), are designed for the first time in a 16nm CMOS FinFET technology and their performance is compared on basis of post-layout simulations. All the DIGOTAs operate at 300 mV power supply while driving a capacitive load of 350 pF. The standard DIGOTA presented the lowest silicon area (44 μm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) and a power consumption of 99.4 nW at 59 kHz Gain-Bandwidth Product (GBW). The ST-DIGOTA achieved the highest DC gain of 43.9 dB, at the cost of a 6X increased power (609 nW) and 14% larger area, while the FI-DIGOTA achieves the highest GBW (100.3 kHz) and Slew Rate (8 mV/μs) at 36X more power (3.67 μW) and 2.5x larger are than the standard DIGOTA.According to these results, an area-normalized large signal figure of merit (IFOM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LA</inf>) of 117k, 19.2k and 1.8k (mV/μs)•pF/(nA• mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) was accomplished along with an area-normalized small signal figure of merit (IFOM<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SA</inf>) of 1.42M, 236k and 23.6k kHz •pF/(nA•mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) for the DIGOTA, ST-DIGOTA and FI-DIGOTA, respectively, where the first two topologies surpass the current state of the art.