A 23–29 GHz 3-stack Power Amplifier in 22nm FD-SOI CMOS Technology

A 23–29 GHz power amplifier (PA) based on a stacked field-effect transistor (FET) topology is proposed. To achieve higher output power and gain, the output stage employs a triple-stacked FET design. To improve stacking efficiency, neutralization capacitors are added between the differential common-source (CS) amplifiers to compensate for phase mismatches at the stack nodes. Round-table and vertical gate repetition techniques are applied to achieve a compact layout and enhance the PA’s power density. The proposed PA is fabricated using the 22nm FD-SOI process. Measurement results show that the proposed PA delivers a peak saturated power (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</inf>) of 19.6 dBm, with a core area of only 0.047 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, achieving a power density of 1936.2 mW/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.