Accelerating Comprehensive Specification Optimization of Analog Circuits Using Transient Assertions and Graph Neural Networks

As the design specifications for circuits become increasingly stringent, the demand for automation and intelligence in the sizing of analog integrated circuits (ICs) continues to grow. Algorithms are required to complete circuit optimization tasks under more comprehensive specifications. In this paper, we propose a transferable pole-zero-based transient assertion (PZTA) system. It minimizes the number of high-time-cost transient (Tran) simulations by asserting the stability of the circuit. Furthermore, we utilize a relational graph convolutional network (RGCN) as a function approximator within a reinforcement learning (RL) framework to extract more topological information from the circuits. Experimental results based on the open-source testing suite AnalogGym demonstrate that compared to RGC-NRL before and after embedding the PZTA system, the number of Tran simulations was reduced by 75.68%. Additionally, the assertion accuracy of the model achieved 99.57%.