A Pipelined-SAR ADC with a Compensation-Free Two-Stage Amplifier

This paper presents a 1 GS/s, 10-bit pipelined-SAR ADC with a proposed two-stage amplifier that no need frequency compensation. The proposed amplifier mimics the three-stage ring amplifiers. With the transmission gates adopted in the first stage, the voltage drop creates a dead-zone that biases the output stage in the subthreshold region, providing stability. Fabricated in a TSMC 28-nm technology, the proposed ADC achieves a SNDR of 52.01 dB under 1 GS/s sampling rate, while consuming only 7.99 mW.