A high-PSRR and low-noise CMOS-based reference with barrel shifting and notch filtering

This work presents a fully integrated, low-noise, CMOS reference generator capable of operating at supply voltages from 0.7 V up to 1.5 V. A 3-phase barrel shifting technique is proposed to upconvert the flicker noise, achieving an integrated noise of 19.7 μV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> over a 10 kHz bandwidth under typical conditions (0.7 V, 27 °C), without needing bulky off-chip filters. The untrimmed reference voltage from post-layout simulations exhibits an average temperature drift of 30 ppm/°C across the full temperature range of -40 °C to 125 °C. A 2-stage switched-capacitor notch filter that is proposed, brings a 60-fold reduction in the upconverted voltage ripple, and a 40 dB reduction in thermal noise at 10kHz while resulting in an exceptional Power Supply Rejection Ratio (PSRR) of -95 dB at 50 Hz. The circuit is implemented in a 22-nm FDSOI process, occupying an area of only 0.01 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while consuming a power of 288 nW at the typical condition.